Phase locked loops (PLL) are useful building tools available from several manufacturers as a single integrated circuit. A typical PLL is shown in FIG. 1 and incorporates a phase frequency detector (100), a charge pump (110), a low pass filter element (120) and a voltage controlled oscillator (VCO) (130). A clock signal Rclk is provided as a first input to the phase detector (100) and a feedback signal, Nclk, the output of a frequency divider, is provided as a second input. In this known phase locked loop, PLL, based frequency synthesiser, the outputs of the tri-state phase/frequency detector, PFD (100), are used to drive the charge pump (110).
Although shown as an integer- N PLL in FIG. 1, such PLL's can be modified to fractional -N by using an interpolator to control the frequency divider. The tri-state PFD has particular application for fractional-N frequency fractional synthesis, as noisy digital activity may be performed while the PFD is in it's off state. However, the use of the these PFD in fractional-N phase detectors suffers from a problem associated with its non-linearity behaviour around the origin. Other types of phase detectors (e.g. XOR based) do not suffer from problems associated with non-linearity problems, but do have other problems that obviate their effectiveness in use in these applications. If the problem of non-linearity could be overcome the PFD would be the preferred detector for the fractional-N PLL application.
FIG. 2 details the PFD (100) that can be used in the circuitry of FIG. 1. It comprises two D-type flip-flops (201, 202), the D input of both being tied to a logic high. A reference frequency Rclk clocks a first flip-flop (201) and a signal frequency Nclk clocks the second flip-flop (202). The outputs of both flip flops are input to an AND gate (203), the output of which is the input to a delay element (204), the output of which is then input to the reset input of both flip-flops (201, 202). It will be understood that both flip flops are therefore provided with the same signal to their respective reset inputs. The effect of this input from the AND gate (203) and delay element (204) ensures that the output of each flip-flop has a minimum pulse width. The output of each flip-flops drives an individual charge pump (205, 206), the charge pumps being connected at a common node (207) that provides the output, Icp, of the circuit, the output, Icp, being the combination of current from the first and second charge pumps.
The charge pump output, Icp, can have three states, “up” active, “down” active and “off”, the states being driven from the outputs of the flip-flops of the PFD. When “up” is active Icp sources current Icp (205). When “down” is active, Icp sinks current Idn (206). When neither pump-up (205) nor pump-down (206) is active, Icp is zero so the charge pump is in the “off”state. If Iup and Idn are perfectly matched then Icp is also zero when both pump-up and pump-down are active.
It will be understood therefore that the PFD/charge pump combination outputs a net pulse of source current, Iup, if the Nclk phase lags the Rclk phase, the pulse width being proportional to the phase difference between the two signals. Similarly, a net sink current pulse, Idn, is output if the Nclk phase leads the Rclk phase, again of width proportional to the phase error.
In any cycle, the presence of the delay element (204) ensures that both “up” and “down” outputs of the PFD circuitry are active for at least the period τ (known as the anti-backlash delay), before the flip-flops are reset. This ensures that there is no dead-zone in the phase detector when the phase error is very small. The anti-backlash delay is typically chosen to be at least as long as the turn-on time of the current sources. A timing diagram shown in FIG. 3 illustrates an example where the Nclk phase leads the Rclk phase, i.e. the VCO output frequency is too high. The net result is that a negative current pulse, of width proportional to the input phase error, is output (Icp) from the charge pump which acts to slow down the VCO output frequency. When the PLL is in lock with small phase error, the tri-state charge pump is only on for the anti-backlash period, which is typically a small fraction of the reference period. This gives the tri-state PFD good immunity to substrate noise.
As seen in FIG. 1, the output of this circuitry is low pass filtered (120) before driving the VCO (130), the frequency divided output of which is used as the feedback loop signal and the input Nclk to the second flip flop (202). The presence of a positive or negative pulse from the phase detection circuitry causes the VCO (130) to change frequency and phase until Rclk=Nclk in both frequency and phase. The output of the phase detection circuitry is therefore adopting a zero value and the VCO (130) is locked onto that frequency.
As discussed previously, the integer -N circuitry may be modified to form a fractional-N PLL, such as that shown in FIG. 4. The same reference numerals are used for similar components. Such a circuit incorporates a fractional interpolator (401) to control the N divider (402) in the feedback loop. Typically, an interpolator such as a sigma-delta modulator with an output containing a DC component equal to the interpolated fractional value and an error component high pass shaped versus frequency is used to effect a modulation of the phase of the Nclk edge at the PFD input in such a way that its average value is equal to the phase of reference input to the PFD, and with noise shaping in the modulator ensuring that quantised phase noise is shaped to have a high frequency characteristic which is subsequently attenuated by the low pass loop filter (120). A typical PFD/charge pump transfer function is shown in FIG. 5. Positive output charge corresponds to net “up” current out of the charge pump, negative output charge corresponds to net “down” current. Mismatch between the “up” and “down” charge pump currents causes a non-linearity in the PFD/charge pump transfer function in the region of the zero input phase error point. This non-linearity generates harmonics of the shaped quantised phase noise signal on Nclk, which can alias down in-band when sub-sampled at the PFD reference rate. The aliased quantisation noise typically looks like discrete spurs at frequencies of multiples and sub-multiples of the reference frequency divided by the modulus of the interpolator. With dither added to the interpolator, the aliased frequencies spread out into finer frequency bins and looks more like broad-band noise, which results in degraded phase noise performance out of the synthesiser.
In order to obviate this problem it is possible to utilise a charge pump with sufficiently low mis-match so that the aliasing effect is negligible. Such a charge pump is however costly to make. An alternative solution is to add a fixed phase offset to the input phase error signal so that operation of the PFD and charge pump is biased away from the zero phase point, thus avoiding the non-linearity region.
The offset should be large enough to ensure that the Nclk edge modulates either the width of the “up” pulse OR the width of the “down” pulse and not ever both. When the Nclk edge location is modulated by the sigma-delta modulator, the offset should be greater than the largest phase deviation effected by the sigma-delta output from its average output value. For example, a suitable fractional interpolator such as a 3rd order MASH sigma-delta modulator generating interpolated fractional values between 0 and 1, outputs, once every clock cycle, one of eight integer values that can lie in the range −3 to +4 inclusive. This implies that the worse case deviation of an Nclk edge around its nominal edge location is within +/−4 RF clock cycles and hence an input phase offset in the PFD, that corresponds to 4 RF clock cycles should be sufficient.
The aforementioned PFD problem is specific to fractional-N PLL's. Prior art PFD structures tend to address additional problems and examples are described in Chapter 5 of Frequency Synthesis By Phase Lock: William F Egan 2nd Edition Wiley Interscience which refers to dead-zone and cross over problems that are characteristic of standard tri-state PFD architecture when operating close to the zero phase error point. If the phase detector's operating point moves into the dead-zone region the loop is effectively open and this results in a large increase in noise at the VCO output. Just out-side this dead-zone region the detector's gain response is highly non-linear. As the input error increases the detector's gain linearity improves as in this case the up or down pulses are wide enough to turn the current sources on to their final value, producing a net output charge proportional to the input phase error.
A widely used solution to the dead-zone problem is to insert a delay, t, in the reset path to both flip-flops as shown in FIG. 2. This is what is shown in FIG. 2 and its operation has been described above. The key idea here is to ensure that, near zero phase difference, both current source outputs are produced rather than neither. This always produces an output response, which is the difference between the up and down current pulses.
This solution for eliminating the dead-zone works well for an Integer-N PLL where monotonicity rather than linearity in the phase detector transfer function is sufficient to maintain low noise performance. Up/down current mismatch does, however, cause reference spur side-bands to appear around the PLL output frequency. In an Integer-N PLL the reference may only be a decade above the loop bandwidth and thus reference spurs will see limited attenuation by the low pass loop filter response. Reference spurs are much less of an issue in a fractional-N synthesizer as the much higher offset reference spurs are greatly attenuated by the loop. However, the non-linearity due to mismatch poses a problem specific to fractional-N, particularly when a high order noise shaping based fractional interpolator is used. The non-linearity causes harmonic distortion of the noise shaped phase signal on the Nclk input to the PFD and these harmonic distortion products can alias down inside the loop bandwidth due to the sub-sampling operation of the PFD.
Egan describes alternative solutions other than inserting the anti-backlash delay 30 element, to the deadzone and cross over distortion problem. One of these is the use of a constant bleed current, such as that shown in FIG. 6, as a solution to the crossover distortion problem. This works on the principle that, when the PFD is inside a PLL, the feedback loop acts to bring the average phase detector output to zero, hence a phase offset will be produced at the input to the PFD so that an appropriate opposite polarity pulse of current is output to cancel, on average, the charge due to the constant bleed current. Thus, steady state operation of the phase detector in the PLL is biased away from the zero phase error point, thus avoiding the cross-over distortion problems.
While the average or DC output of the detector is zero, the constant bleed along with the regular pulse of correction current will produce an AC error signal at the detector output. This AC signal will have a strong fundamental component at the reference frequency and lower magnitude components at harmonics of the reference frequency all of which will produce FM spur side-bands at the PLL output. The strong fundamental component produced by this constant bleed method is the most troublesome as this gets the least attenuation from the loop filter.
Egan further refers to U.S. Pat. No. 4,970,475 of Gillig the disclosure of which is incorporated herein by way of reference and which describes a pulsed bleed solution to the cross-over distortion problem which works in a similar way to the constant bleed solution, but with a reduced spur component at the reference fundamental frequency. An example of such a circuit is shown in FIG. 3 of Gillig. In this circuit two flip flops are provided, the inputs to both flip flops being tied to a logic high. The first flip flop is clocked with a reference signal whereas the second flip flop is clocked with a variable frequency feedback signal. The outputs of the flip flops are ANDed and the resulting AND gate output delayed by a delay element. The output of the delay element is then used to reset one of the flip flops while the output of the AND gate prior to the delay element is used to reset the other flip flop. Each of the flip flop outputs is used to enable a charge pump—a negative polarity source and a positive polarity source, the output of the circuit being the common node between the two charge pumps. The circuit maintains a lock condition in a phase locked loop by extending the DOWN pulse enabling the negative polarity charge pump to the same width as the UP pulse that enables the positive pump; thereby creating a net zero charge.
Alternative embodiments to the solution addressed by Gillig are shown in FIGS. 6, 7 and 9 (also shown in FIG. 5.36 of Egan) of his Patent by introducing an equal delay in the path controlling the correcting current. This additional delay causes the correcting pulse to overlap with the bleed pulse in time so that the residual output is minimised, thus reducing the reference spur component further. This is a significant improvement in an integer-N PLL but is much less so in a fractional- N PLL. This is because in the fractional -N PLL, the residual spurs in the illustrated example of FIG. 3 of Gillig tend to be already sufficiently attenuated by the loop.
As well as being solutions to the dead-zone and cross over distortion problems, as described by Egan, this input phase offset produced by either the constant bleed or the pulsed bleed implementation of Gillig provides a way to avoid the up/down mismatch non-linearity that causes aliased in-band noise in a fractional-N PLL. If the phase offset is larger than the peak phase deviation on the Nclk edge, then the Nclk edge modulates either the up or down current pulse width, but not both. The constant bleed current method carries additional broad-band noise and the fact that it is on over the complete reference cycle means that it is to susceptible to noise and interference pick-up.
Of particular concern, specific to a fractional-N synthesizer, is noise coupling from the fractional interpolator circuitry when it is on the same substrate as the charge pump circuit. While the noise shaped output of the interpolator has a spectrum with little energy inside the loop bandwidth, the digital switching activity internally in the interpolator has significant energy in its spectrum at frequencies lower than the PLL bandwidth. Substrate noise arising from switching activity at these frequencies couples through to the charge pump while Icp is on, resulting in noise side-bands appearing around the carrier at offsets equal to the noise frequency. Hence, it will be appreciated that the always on bleed current solution, while reducing the level of aliased spurs, can increase the overall in-band noise and spur level due to substrate coupling. The inherent noise produced by the bleed current device also adds to the in-band noise.
The implementation of FIG. 3 of Gillig is an improvement on constant bleed because the pulsed bleed current source is only active for a fraction of a reference cycle which means it's broad-band noise contribution will be lower. However, because the reset to the reference flip-flop is delayed, the PLL will act to force the phase of Fv (or Nclk) to lead the reference (or Rclk). The implication of this is that the potential for interference from the interpolator, (the activity of which is triggered from the Nclk edge), getting into the charge pump is maximised. This hazard is illustrated in the timing diagram of FIG. 7.
There is therefore a requirement for a device that provides an alternative solution to the the problems addressed by the bleed current and the Gillig solutions, and which does not substantially effect an incrementation of noise within the circuitry.